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| www.fairchildsemi.com FMS3818 Triple Video D/A Converters 3 x 8 bit, 180 Ms/s Features * * * * * 2.5% gain matching 0.5 LSB linearity error Internal bandgap voltage reference Low glitch energy Single 3.3 Volt power supply Description The FMS3818 is a low-cost triple D/A converter, tailored to fit graphics and video applications where speed is critical. CMOS-level inputs are converted to analog current outputs that can drive 25-37.5 loads corresponding to doubly-terminated 50-75 loads. A sync current following SYNC input timing is added to the IOG output. BLANK will override RGB inputs, setting IOG, IOB and IOR currents to zero when BLANK = L. Although appropriate for many applications the internal 1.25V reference voltage can be overridden by the VREF input. Few external components are required, just the current reference resistor, current output load resistors, bypass capacitors and decoupling capacitors. Package is a 48-lead LQFP. Fabrication technology is CMOS. Performance is guaranteed from 0 to 70C. Applications * PC Graphics * Video signal conversion - RGB - YCBCR - Composite, Y, C Block Diagram SYNC BLANK SYNC IOS G7-0 8 8 bit D/A Converter IOG B7-0 8 8 bit D/A Converter IOB R7-0 CLK 8 8 bit D/A Converter IOR COMP RREF VREF +1.25V Ref REV. 1.2.3 December 2004 FMS3818 DATA SHEET Functional Description Within the FMS3818 are three identical 8-bit D/A converters, each with a current source output. External loads are required to convert these currents to voltage outputs. Data inputs RGB7-0 are overridden by the BLANK input. SYNC = H activates sync current from IOS for sync-ongreen video signals. VDDA IOS SYNC G7-0 VDDA BLANK gates the D/A inputs. If BLANK = H, the D/A inputs control the output currents to be added to the output blanking level. If BLANK = L, data inputs and the pedestal are disabled. D/A Outputs Each D/A output is a current source from the VDDA supply. Expressed in current units, the GBR transformation from data to current is as follows: G = G7-0 & BLANK + SYNC * 112 B = B7-0 & BLANK R = R7-0 & BLANK Typical LSB current step is 73.2 A. VDDA B7-0 To obtain a voltage output, a resistor must be connected to ground. Output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor connected between RREF and GND. To implement a doubly-terminated 75 transmission line, a shunt 75 resistor should be placed adjacent to the analog output pin. With a terminated 75 line connected to the analog output, the load on the FMS3818 current source is 37.5. The FMS3818 may also be operated with a single 75 Ohm terminating resistor. To lower the output voltage swing to the desired range, the nominal value of the RREF resistor should be doubled. VDDA R7-0 Figure 1. FMS3818 Current Source Structure Voltage Reference Full scale current is a multiple of the current ISET through an external resistor, RSET connected between the RREF pin and GND. Voltage across RSET is the reference voltage, VREF, which can be derived from either the 1.25 volt internal bandgap reference or an external voltage reference connected to VREF. To minimize noise, a 0.1F capacitor should be connected between VREF and ground. ISET is mirrored to each of the GBR output current sources. To minimize noise, a 0.1F capacitor should be connected between the COMP pin and the analog supply voltage VDDA. Digital Inputs Incoming GBR data is registered on the rising edge of the clock input, CLK. Analog outputs follow the rising edge of CLK after a delay, tDO. SYNC and BLANK SYNC and BLANK inputs control the output level (Figure 1 and Table 1) of the D/A converters during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC = L turns off a current source, IOS that is connected to the green D/A converter. SYNC = H adds a 112/256 fraction of full-scale current to the green output. SYNC = L extinguishes the sync current during the sync tip. Power and Ground Required power is a single +3.3 Volt supply. To minimize power supply induced noise, analog +3.3V should be connected to VDDD and VDDA pins with 0.1 and 0.01 F decoupling capacitors placed adjacent to each VDD pin or pin pair. High slew-rate digital data makes capacitive coupling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins should be connected to a common solid ground plane for best performance. REV. 1.2.3 December 2004 data: 700 mV max. sync: 307 mV Figure 2. Nominal Output Levels 2 DATA SHEET FMS3818 Table 1. Output Voltage Coding VREF = 1.25 V, RREF = 348 , RL = 37.5 RGB7-0 (MSB...LSB) 1111 1111 1111 1111 1111 1110 1111 1101 * * 1000 0000 0111 1111 0111 1111 * * 0000 0010 0000 0001 0000 0000 0000 0000 XXXX XXXX XXXX XXXX SYNC 1 0 1 1 * * 1 1 0 * * 1 1 1 0 1 0 BLANK 1 1 1 1 * * 1 1 1 * * 1 1 1 1 0 0 VRED, VBLUE (mV) 700 700 697 695 * * 351 349 349 * * 5 3 0 0 0 0 VGREEN (mV) 1,007 700 1,004 1,001 * * 658 656 349 * * 312 310 307 0 307 0 Pin Assignments LQFP Package GND R7 R6 R5 R4 R3 R2 R1 R0 GND GND NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND G0 G1 G2 G3 G4 G5 G6 G7 BLANK SYNC VDDD 1 2 3 4 5 6 7 8 9 10 11 12 FMS3818 RREF VREF COMP IOR IOG VDDA VDDA IOB GND GND CLK NC NC GND GND B0 B1 B2 B3 B4 B5 B6 B7 NC 13 14 15 16 17 18 19 20 21 22 23 24 REV. 1.2.3 December 2004 3 FMS3818 DATA SHEET Pin Descriptions Pin Name CLK Pin Number 26 Value CMOS Pin Function Description Clock Input. Pixel data is registered on the rising edge of CLK. CLK should be driven by a dedicated buffer to avoid reflection induced jitter, overshoot, and undershoot. Red, Green, and Blue Pixel Data Inputs. RGB digital inputs are registered on the rising edge of CLK. Clock and Data Inputs R7-0 G7-0 B7-0 Controls SYNC 47-40 9-2 23-16 11 CMOS CMOS Sync Pulse Input. Bringing SYNC LOW, disables a current source which superimposes a sync pulse on the IOG output. SYNC and pixel data are registered on the rising edge of CLK. SYNC does not override any other data and should be used only during the blanking interval. If sync pulses are not required, SYNC should be connected to GND. Blanking Input. When BLANK is LOW, pixel data inputs are ignored and the D/A converter outputs are driven to the blanking level. BLANK is registered on the rising edge of CLK. Red, Green, and Blue Current Outputs. Current source outputs can drive VESA VSIS, and RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Sync pulses can be added to the green output. When SYNC is HIGH, the current added to IOG is: IOS = 2.33 (VREF / RREF) BLANK 10 CMOS Video Outputs IOR IOG IOB 33 32 29 0.700 Vp-p Voltage Reference VREF 35 +1.25 V Voltage Reference Input/Output. Internal 1.25V voltage reference is available on this pin. An external +1.25 Volt reference may be applied to this pin to override the internal reference. Decoupling VREF to GND with a 0.1F ceramic capacitor is required. Current-set Resistor Node. Full-scale output current of each D/A converter is determined by the value of the resistor connected between RREF and GND. Nominal value of RREF is found from: RREF = 5.31 (VREF/IFS) where IFS is the full-scale output current (amps) from the D/A converter (without sync). Sync is 0.439 IFS. D/A full-scale current may also be calculated from: IFS = VFS/RL Where VFS is the full-scale voltage level and RL is the total resistive load (ohms) on each D/A converter. COMP 34 0.1 F Compensation Capacitor Node. A 0.1 F ceramic capacitor must be connected between COMP and VDD to stabilize internal bias circuitry. RREF 36 348 4 REV. 1.2.3 December 2004 DATA SHEET FMS3818 Pin Descriptions (continued) Pin Name VDDA VDDD GND NC Pin Number 30, 31 12 1, 14, 15, 27, 28, 38, 39, 48 13, 24, 25, 37 Value +3.3V +3.3V 0.0V -- Pin Function Description Analog Supply Voltage. Digital Supply Voltage. Ground. No Connect Power, Ground REV. 1.2.3 December 2004 5 FMS3818 DATA SHEET Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Power Supply Voltage VDDA (Measured to GND) VDDD (Measured to GND) Digital Inputs Applied Voltage (Measured to GND)2 Forced Current3,4 Analog Inputs Applied Voltage (Measured to GND)2 Forced Current3,4 Analog Outputs Applied Voltage (Measured to GND)2 Forced Current Temperature Operating, Ambient Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage -65 -20 110 150 300 220 150 C C C C C 3,4 Min -0.5 -0.5 -0.5 -5.0 -0.5 -10.0 -0.5 -60.0 Typ Max 4 4 VDDD + 0.5 5.0 VDDA + 0.5 10.0 VDDA + 0.5 60.0 unlimited Unit V V V mA V mA V mA sec. Short Circuit Duration (single output in HIGH state to ground) Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Operating Conditions Parameter VDD VREF CC RL TA Power Supply Voltage Reference Voltage, External Compensation Capacitor Output Load Ambient Temperature, Still Air 0 Min 3.0 1.0 Nom 3.3 1.25 0.1 37.5 70 Max 3.6 1.5 Units V V F C Test Rank Definitions Rank P D C T Production tested at 25C. Guaranteed by design over full temperature range. Guaranteed by characterization and design over full temperature range. Target specification, pending characterization. 6 REV. 1.2.3 December 2004 DATA SHEET FMS3818 Electrical Characteristics1 Parameter Power Supply Currents IDD Supply Current Power Dissipation Digital Inputs VIH VIL IIH IIL CI Input Voltage, HIGH Input Voltage, LOW Input Current, HIGH Input Current, LOW Input Capacitance Output Current RO CO VREF Output Resistance Output Capacitance Output Voltage Temperature Coefficient Full Full Full Full 25C 25C 25C 25C Full Full PC PC PC PC D PC C D PC CT 1.135 40 7 1.25 1.365 -1 -1 4 30 2.5 0.8 +1 +1 V V A A pF mA k pF V ppm/C FMS3818 FMS3818 25C Full Full P C D 80 90 300 mW mA Temp Test Rank Min Typ Max Unit Analog Outputs Reference Output Note: 1. Specified under normal operation conditions: VDDA = VDDD = 3.3V with external 1.25V reference. Switching Characteristics1 Parameter Clock Input Conversion rate tPWH tPWL tS tH Pulse-width HIGH Pulse-width LOW Setup Hold FMS3818 FMS3818 FMS3818 FMS3818 Data Outputs2 tD tR tF tSET tSKEW Clock to Output Delay Rise Time Fall Time Settling Time Skew Full Full Full C C C C C 1.6 0.6 0.4 2.5 0.3 ns ns ns ns ns FMS3818 Full Full Full 25C Full 25C Full C C C P C P C 2 2 1.5 2 0.6 0.6 180 Ms/s ns ns ns ns ns ns Temp Test Rank Min Typ Max Unit Data Inputs Notes: 1. Specified under normal operation conditions: VDDA = VDDD = 3.3V with external 1.25V reference. 2. With 50 doubly terminated load with internal 1.25V reference. REV. 1.2.3 December 2004 7 FMS3818 DATA SHEET DC Performance1 Parameter Resolution DNL INL Differential Non-Linearity Error Integral Non-Linearity Error Offset Error Gain Matching Error Absolute Gain Error 1 Temp Full 25C Full 25C Full Full Full Full Full 25C Full Full Test Rank D P C P C PC PC PC C P PC C Min 8 -0.5 -0.5 -0.5 -0.5 -2.5 -3.5 18.0 Typ1 Max +0.5 +0.5 +0.5 +0.5 0.01 +2.5 +3.5 Unit bits LSB LSB %FS %FS %FS mA mA Full-scale Output Current1 Full-scale Output Current PSRR Thermal JC JA Resistance, Junction-to-Case Resistance, Junction-to-Ambient 2 18.7 18.7 19.4 Power Supply Rejection Ratio (DC) -0.01 0 +0.01 %/% C /W D 91 C /W Notes: 1. Specified under normal operation conditions: VDDA = VDDD = 3.3V with external 1.25V reference. RREF = 348. 2. With internal reference. Trim RSET to calibrate full-scale current. AC Performance1 Parameter Analog Outputs Glitch Energy DAC-to-DAC Crosstalk Data Feedthrough Clock Feedthrough 7 25C 25C 25C C C C C 20 30 50 60 pVsec dB dB dB Temp Test Rank Min Typ1 Max Unit Note: 1. Specified under normal operation conditions: VDDA = VDDD = 3.3V with external 1.25V reference. 8 REV. 1.2.3 December 2004 DATA SHEET FMS3818 Timing Diagram tPWL CLK tPWH 1/fS tS PIXEL DATA & CONTROLS DataN tH DataN+1 DataN+2 3%/FS 90% tD OUTPUT 50% tSET tF 10% tR Applications Information Figure 4 illustrates a typical FMS3818 interface circuit. In this example, an optional 1.2 Volt bandgap reference is connected to the VREF output, overriding the internal voltage reference source. 2. Grounding It is important that the FMS3818 power supply is well-regulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. The FMS3818 has separate analog and digital circuits. To keep digital system noise away from the D/A converter, it is recommended that power supply voltages come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. 3. The power plane for the FMS3818 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the FMS3818 is the same as that of the system's digital circuitry, power to the FMS3818 should be decoupled with 0.1F and 0.01F capacitors and isolated with a ferrite bead. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. If the digital power supply has a dedicated power plane layer, it should not be placed under the FMS3818, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the FMS3818 and its related analog circuitry can have an adverse effect on performance. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. 4. Printed Circuit Board Layout Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VREF, IREF, COMP, IOS, IOR, IOG) as short as possible and as far as possible from all digital signals. The FMS3818 should be located near the board edge, close to the analog output connectors. 5. Improved Transition Times Output shunt capacitance dominates slowing of output transition times, whereas series inductance causes a small amount of ringing that affects overshoot and settling time. With a doubly terminated 75 load, transition times can be improved by matching the capacitive impedance output of the FMS3818. Output capacitance can be matched with a 220 nH inductor in series with the 75 source termination. REV. 1.2.3 December 2004 9 FMS3818 DATA SHEET U1 FMS3818 IOG 32 W1 COAX R1 75 IOB 29 W2 COAX R2 75 IOR 33 W3 COAX R3 75 L1 220nH L2 220nH L3 220nH R4 75 R5 75 R6 75 Figure 3. Schematic, FMS3818 Transition Time Sharpening Circuit A 220 nH inductor trims the performance of a 4 ft cable, quite well. In Figures 4 through 7, the glitch at 12.5 ns, is due to a reflection from the source. Not shown, are smaller glitches at 25 and 37.5 ns, corresponding to secondary and tertiary reflections. Inductor values should be selected to match the length and type of the cable. 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -5.00 0.00 5.00 10.00 15.00 20.00 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -5.00 Rout (V) Gout (V) 0.00 5.00 10.00 15.00 20.00 Time (ns) Time (ns) Figure 4. Unmatched tR. Figure 5. Matched tR. 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -5.00 0.00 5.00 10.00 15.00 20.00 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -5.00 Rout (V) Gout (V) 0.00 5.00 10.00 15.00 20.00 Time (ns) Time (ns) Figure 6. Unmatched tF. Figure 7. Matched tF. 10 REV. 1.2.3 December 2004 DATA SHEET FMS3818 +3.3V 0.1 F 0.01F 10 F 0.1F VDDD RED PIXEL INPUT GREEN PIXEL INPUT BLUE PIXEL INPUT CLOCK SYNC BLANK R7-0 G7-0 B7-0 CLK SYNC BLANK GND VDDA Red IOR IOG FMS38XX Triple 8-bit D/A Converter COMP 0.1F VREF RREF 348 LM185-1.2 (Optional) 0.1F IOB 75 75 75 VDDA 3.3k (only required with external reference) ZO=75 75 75 75 Green w/Sync ZO=75 Blue ZO=75 Figure 8. Typical Interface Circuit Related Products * FMS3110/3115 Triple 10-bit 150 Msps D/A Converters * FMS9884A 3 x 8 bit 140 Ms/s A/D Converter REV. 1.2.3 December 2004 11 FMS3818 DATA SHEET Mechanical Dimensions 48-Lead LQFP Package Inches Min. A A1 A2 B D/E D1/E1 e L N ND ccc Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Pin 1 identifier is optional. 7 2 6 4 5 4. Dimension N: Number of terminals. 5. Dimension ND: Number of terminals per package edge. 6. "L" is the length of terminal for soldering to a substrate. 7. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum B dimension by more than 0.08mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm. Symbol .055 .063 .001 .005 .053 .057 .006 .010 .346 .362 .268 .284 .019 BSC .017 .029 48 12 0 7 .004 1.40 1.60 .05 .15 1.35 1.45 .17 .27 8.8 9.2 6.8 7.2 .50 BSC .45 .75 48 12 0 7 0.08 D D1 e E E1 PIN 1 IDENTIFIER C L 0.063" Ref (1.60mm) See Lead Detail A A2 B A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C 12 REV. 1.2.3 December 2004 FMS3818 DATA SHEET Ordering Information Product Number FMS3818KRC FMS3818KRC_NL Conversion Rate 180 Ms/s 180 Ms/s Yes Lead Free Temperature Range 0C to 70C 0C to 70C Screening Commercial Commercial Package 48-Lead LQFP 48-Lead LQFP Package Marking 3818KRC 3818KRC NL DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 2001 Fairchild Semiconductor Corporation |
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